With ever increasing use of portable devices such as cellular phones and digital cameras, a non-insulated, step-down type switching regulator (hereinafter referred to as switching regulator) is utilized more often incorporated into circuits of power supply. This switching regulator is known to be highly efficient for operation and suitable for downsizing the devices.
Although the switching regulator is highly efficient for rated load, its efficiency considerably decreases when load devices are in the low current consumption mode such as at stand-by state or sleep mode since the switching regulator itself has a relatively high current consumption.
This difficulty has been obviated by terminating the operation of the switching regulator at stand-by state or sleep mode, and then either supplying battery voltages directly to the devices or switching to a series regulator which can operate at low currents.
A stabilized DC (direct current) power supply has been disclosed, which is capable of reducing power consumption by selectively switching to either switching regulator or series regulator depending on the amount of the load, for example, to which a current is supplied (for example, Japanese Laid-Open Patent Application No. 2003-216247).
A stabilized DC power supply is illustrated in FIG. 5, which is configured to terminate the operation of a switching regulator during the period at stand-by state or sleep mode, and subsequently switch to a series regulator which can operate at low current consumption.
FIG. 5 illustrates a schematic circuit diagram of the stabilized DC current supply previously known, which can operate in reduced power consumption by selectively switching to either a switching regulator 1 or a series regulator 2 depending on the magnitude of the circuit load. FIG. 6 is a timing diagram illustrating the operation of the switching regulator circuit of FIG. 5.
Referring now to FIG. 5, an inductor L1 is connected between a terminal Lx of DC/DC converter 10, which is included in the switching regulator 1, and an output terminal Vout of the switching regulator 1, and a capacitor C1 is connected between the output terminal Vout and the ground (GND).
From the output terminal Vout, power is supplied to a load. In addition, further power is supplied from an output terminal VRout of the series regulator 2. The inductor L1 and the capacitor C1 thus constitute a smoothing circuit and the capacitor C1 also serves to stabilize the output voltage VRout from the series regulator 2.
A DC power source (not shown) is connected between a power terminal Vdd of a DC—DC converter 10 and the ground GND. Similarly, a further DC power source is also connected between a power terminal Vdd of the series regulator 2 and the ground GND.
In addition, the stabilized DC current supply is controlled by a main portion (not shown) of the device as a load such that the switching regulator and the series regulator are suitably switched selectively when a portable device is in the low current consumption mode such as at stand-by state or sleep mode.
The switching regulator 1 includes at least a first switching element 11 with an input terminal for receiving source voltage Vdd, a second switching element 12 for use in synchronous rectification, the inductor L1, the capacitor C1, a Pch drive circuit 13 configured to drive the first switching element 11, and an Nch drive circuit 14 configured to drive the second switching element 12.
The Pch drive circuit 13 includes a three-input NOR circuit 13a and an inverter (INV) 13b. The Nch drive circuit 14 includes a three-input NAND circuit 14a and a further inverter 14b. 
The switching regulator 1 further includes two serial resistors R1 and R2 for outputting the voltage proportional to output voltage VRout, a third switching element 21 for interrupting the current flowing through the serial resistors, a digital-to-analogue converter (DAC) 16 for generating a reference voltage Vref, an operational amplifier (AMP) 17 for amplifying the voltage difference between the voltage (A) proportional to output voltage Vout and a reference voltage Vref, an oscillator circuit (OSC) 15 for outputting triangle waves of voltage (or triangular-wave voltage), a comparator (CMP) 18 for outputting square waves based on the comparison between the output voltage from operational amplifier (AMP) 17 and the triangular-wave voltage, and a control circuit 20 configured to output control signals for controlling start/stop operation of the switching regulator 1 after receiving sleep signals (SPLb) output from the main portion of the device main (not shown).
To the three-input NOR circuit 13a and NAND circuit 14a, the output from comparator (CMP) 18 and a second start signal (DRV) from control circuit 20 are applied, respectively.
Furthermore, a voltage (NLS) is applied to the three-input NOR circuit 13a, which is also applied to the gate of the second switching element 12. In addition, a voltage (PHS) is applied to the three-input NAND circuit 14a, which is also applied to the gate of the first switching element 11.
After receiving the output from comparator (CMP) 18 and the control signal (DRV), the Pch drive circuit 13 and Nch drive circuit 14 carry out ON/OFF control operations of the first switching element 11 and second switching element 12.
As described earlier, a series regulator 2 (VR) is provided for supplying power to the load during the halt period of switching regulator 1 and an output terminal (VRout) of the series regulator 2 (VR) is connected to the output terminal of the switching regulator 1.
The operation of the circuits of FIG. 5 is now described in reference to a timing diagram included in FIG. 6.
At the interval (1) or sleep period, at which sleep signals (SLPb) are at the low level (LO), the control circuit 20 operates to set both a first start signal (ANA) used as chip enable signal and the second start signal, (DRV), (also referred to as the second start voltage or second control signal), at the high level (HI).
The first start signal (ANA) is connected to both the digital-to-analogue converter (DAC) 16 and the enabling terminal (CE) of the oscillator circuit (OSC) 15. During the period of first start signal (ANA) at HI, the operation of both circuits 15, 16 is interrupted, the digital-to-analogue converter (DAC) 16 outputs zero (0) V, and the oscillator circuit (OSC) 15 outputs a source voltage (Vdd).
At the interval (2) where the sleep signals (SLPb) are brought to HI, that is, the sleep mode is lifted and the rated mode operation is initiated, the control circuit 20 operates immediately to set the first start signal (ANA) at LO. On receiving the LO start signal, the digital-to-analogue converter (DAC) 16 operates to output the reference voltage (Vref) and the oscillator circuit (OSC) 15 outputs triangular-wave voltages.
The control circuit 20 then receives the triangular-wave voltages from the oscillator circuit (OSC) 15 and generates synchronization signals (SETb) in synchronous with the triangular-wave voltages.
Subsequently, in synchronous with the falling tail of the first synchronization signal (SETb) formed right after lifting the sleep mode, the second start signal (DRV) is brought to LO and the operation enters the interval (3).
During the period at which the second start signal (DRV) is HI at the intervals (1) and (2), this signal operates, by way of the three-input NOR circuit 13a and inverter (INV) 13b, to maintain the gate voltage (PHS) of the first switching element 11 to be HI and turn off the first switching element 11.
At the same time, this signal also operates to maintain the gate voltage (NLS) of the second switching element 12 to be LO by way of the inverter (INV) 19, three-input NAND circuit 14a, and inverter 14b, and to turn off the second switching element 12.
As a result, the switching regulator 1 remains at halt mode.
At the interval (3) where the second start signal (DRV) is at LO, the three-input NOR circuit 13a and the three-input NAND circuit 14a are both brought to open.
Since the input terminals of the three-input NOR circuit 13a and the three-input NAND circuit 14a are both connected to the output terminal of comparator (CMP) 18, square-wave voltage output from the comparator (CMP) 18 is applied to the gate (PHS) of first switching element 11 and the further gate (NLS) of second switching element 12 by way of the three-input NOR circuit 13a and the three-input NAND circuit 14a. 
As a result, the switching regulator 1 initiates its operation.
During the period where the switching regulator 1 remains at halt mode, however, the output voltage (VRout) from the series regulator 2 (VR) is applied to the output terminal (Vout). In addition, the third switching element 21 is turned off during the period.
As a result, an inverted input voltage (A) of the operational amplifier (AMP) 17 is equal to the output voltage (VRout) from the series regulator 2 (VR) and higher than the reference voltage (Vref) output from digital-to-analogue converter (DAC) 16.
When the second start signal (DRV) is brought to LO, this signal is subsequently applied to the gate of third switching element 21 by way of the inverter (INV) 19. And, this signal operates to turn on the third switching element 21, couple one end of the resistor (R2) to the ground, and decrease the inverted input voltage (A) of the operational amplifier (AMP) 17.
Immediately after the second start signal (DRV) becomes LO, however, the inverted input voltage (A) of the operational amplifier (AMP) 17 still remains as LO.
As a result, the output of the comparator (CMP) 18 becomes HI.
Since the second start signal (DRV) is LO, as described earlier, the three-input NOR circuit 13a and the three-input NAND circuit 14a are both open. In addition, if the output of the comparator (CMP) 18 is also HI during this period, three inputs of the three-input NOR circuit 13a are all brought to HI, although the gate (PHS) of first switching element 11 remains LO. Whereby, the level of the gate (NLS) of second switching element 12 is altered from LO to HI.
As a result, the second switching element 12 is turned on, the output terminal is short circuited through the inductor (L1), and the voltage (Vout) of the output terminal decreases rapidly.
This gives rise to a difficulty of unintentionally resetting several devices connected to the output terminal voltage (Vout) such as a CPU included in load units or a portable device, for example.